From 51ea6fa583fd52eabc5374b414e4052efab4128a Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Thu, 30 May 2019 02:29:24 +0200
Subject: Add Smaxv_V, Sminv_V, Umaxv_V, Uminv_V Inst.; add Tests. (#691)

* Update InstEmitSimdHelper.cs

* Update InstEmitSimdArithmetic.cs

* Update OpCodeTable.cs

* Update CpuTestSimd.cs
---
 ChocolArm64/Instructions/InstEmitSimdHelper.cs | 29 ++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

(limited to 'ChocolArm64/Instructions/InstEmitSimdHelper.cs')

diff --git a/ChocolArm64/Instructions/InstEmitSimdHelper.cs b/ChocolArm64/Instructions/InstEmitSimdHelper.cs
index 2bcda35f..f343dba8 100644
--- a/ChocolArm64/Instructions/InstEmitSimdHelper.cs
+++ b/ChocolArm64/Instructions/InstEmitSimdHelper.cs
@@ -821,6 +821,35 @@ namespace ChocolArm64.Instructions
             }
         }
 
+        public static void EmitVectorAcrossVectorOpSx(ILEmitterCtx context, Action emit)
+        {
+            EmitVectorAcrossVectorOp(context, emit, true);
+        }
+
+        public static void EmitVectorAcrossVectorOpZx(ILEmitterCtx context, Action emit)
+        {
+            EmitVectorAcrossVectorOp(context, emit, false);
+        }
+
+        public static void EmitVectorAcrossVectorOp(ILEmitterCtx context, Action emit, bool signed)
+        {
+            OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
+
+            int bytes = op.GetBitsCount() >> 3;
+            int elems = bytes >> op.Size;
+
+            EmitVectorExtract(context, op.Rn, 0, op.Size, signed);
+
+            for (int index = 1; index < elems; index++)
+            {
+                EmitVectorExtract(context, op.Rn, index, op.Size, signed);
+
+                emit();
+            }
+
+            EmitScalarSet(context, op.Rd, op.Size);
+        }
+
         public static void EmitVectorPairwiseOpF(ILEmitterCtx context, Action emit)
         {
             OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
-- 
cgit v1.2.3