From e674b377104858d5068231dbe395e1038ba5d71d Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Tue, 23 Oct 2018 16:12:45 +0200
Subject: Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to
 half conv. (full FP emu.). Add 4 FP Tests. (#468)

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Superseded.

* Update AInstEmitSimdCvt.cs

* Update ASoftFloat.cs

* Nit.

* Update PackageReferences.

* Update AInstEmitSimdArithmetic.cs

* Update AVectorHelper.cs

* Update ASoftFloat.cs

* Update ASoftFallback.cs

* Update AThreadState.cs

* Create FPType.cs

* Create FPExc.cs

* Create FPCR.cs

* Create FPSR.cs

* Update ARoundMode.cs

* Update APState.cs

* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.

* Nits.
---
 ChocolArm64/Instruction/ASoftFallback.cs | 39 +++++++++++++-------------------
 1 file changed, 16 insertions(+), 23 deletions(-)

(limited to 'ChocolArm64/Instruction/ASoftFallback.cs')

diff --git a/ChocolArm64/Instruction/ASoftFallback.cs b/ChocolArm64/Instruction/ASoftFallback.cs
index 3c5c5c4d..b69e2c75 100644
--- a/ChocolArm64/Instruction/ASoftFallback.cs
+++ b/ChocolArm64/Instruction/ASoftFallback.cs
@@ -112,13 +112,13 @@ namespace ChocolArm64.Instruction
 
             if (op > TMaxValue)
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 return TMaxValue;
             }
             else if (op < TMinValue)
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 return TMinValue;
             }
@@ -137,13 +137,13 @@ namespace ChocolArm64.Instruction
 
             if (op > (long)TMaxValue)
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 return TMaxValue;
             }
             else if (op < (long)TMinValue)
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 return TMinValue;
             }
@@ -161,7 +161,7 @@ namespace ChocolArm64.Instruction
 
             if (op > (ulong)TMaxValue)
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 return TMaxValue;
             }
@@ -179,7 +179,7 @@ namespace ChocolArm64.Instruction
 
             if (op > TMaxValue)
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 return TMaxValue;
             }
@@ -193,7 +193,7 @@ namespace ChocolArm64.Instruction
         {
             if (op == long.MinValue)
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 return long.MaxValue;
             }
@@ -209,7 +209,7 @@ namespace ChocolArm64.Instruction
 
             if ((~(op1 ^ op2) & (op1 ^ Add)) < 0L)
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 if (op1 < 0L)
                 {
@@ -232,7 +232,7 @@ namespace ChocolArm64.Instruction
 
             if ((Add < op1) && (Add < op2))
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 return ulong.MaxValue;
             }
@@ -248,7 +248,7 @@ namespace ChocolArm64.Instruction
 
             if (((op1 ^ op2) & (op1 ^ Sub)) < 0L)
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 if (op1 < 0L)
                 {
@@ -271,7 +271,7 @@ namespace ChocolArm64.Instruction
 
             if (op1 < op2)
             {
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 return ulong.MinValue;
             }
@@ -292,7 +292,7 @@ namespace ChocolArm64.Instruction
 
                 if ((~op2 & Add) < 0L)
                 {
-                    SetFpsrQCFlag(State);
+                    State.SetFpsrFlag(FPSR.QC);
 
                     return long.MaxValue;
                 }
@@ -306,7 +306,7 @@ namespace ChocolArm64.Instruction
                 // op1 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
                 // op2 from (long)ulong.MinValue to long.MaxValue
 
-                SetFpsrQCFlag(State);
+                State.SetFpsrFlag(FPSR.QC);
 
                 return long.MaxValue;
             }
@@ -319,7 +319,7 @@ namespace ChocolArm64.Instruction
 
                 if (Add > (ulong)long.MaxValue)
                 {
-                    SetFpsrQCFlag(State);
+                    State.SetFpsrFlag(FPSR.QC);
 
                     return long.MaxValue;
                 }
@@ -341,7 +341,7 @@ namespace ChocolArm64.Instruction
 
                 if ((Add < (ulong)op1) && (Add < op2))
                 {
-                    SetFpsrQCFlag(State);
+                    State.SetFpsrFlag(FPSR.QC);
 
                     return ulong.MaxValue;
                 }
@@ -366,7 +366,7 @@ namespace ChocolArm64.Instruction
 
                 if (Add < (long)ulong.MinValue)
                 {
-                    SetFpsrQCFlag(State);
+                    State.SetFpsrFlag(FPSR.QC);
 
                     return ulong.MinValue;
                 }
@@ -376,13 +376,6 @@ namespace ChocolArm64.Instruction
                 }
             }
         }
-
-        private static void SetFpsrQCFlag(AThreadState State)
-        {
-            const int QCFlagBit = 27;
-
-            State.Fpsr |= 1 << QCFlagBit;
-        }
 #endregion
 
 #region "Count"
-- 
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