From a0c78f792012cdea060444d7cb6a36dbabb04d52 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sat, 8 Sep 2018 19:24:29 +0200
Subject: Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)

* Update AOpCodeTable.cs

* Update AInstEmitSimdShift.cs

* Update ASoftFallback.cs

* Update AOpCodeSimdShImm.cs

* Update ABitUtils.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Create CpuTestSimdShImm.cs

* Create CpuTestSimdRegElem.cs

* Address PR feedback.

* Nit.

* Nit.
---
 ChocolArm64/Instruction/AInstEmitSimdHelper.cs | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'ChocolArm64/Instruction/AInstEmitSimdHelper.cs')

diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
index 4ecfdae3..cb884c1a 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
@@ -626,6 +626,9 @@ namespace ChocolArm64.Instruction
             int Bytes = Op.GetBitsCount() >> 3;
             int Elems = Bytes >> Op.Size;
 
+            EmitVectorExtract(Context, Op.Rm, Elem, Op.Size, Signed);
+            Context.EmitSttmp();
+
             for (int Index = 0; Index < Elems; Index++)
             {
                 if (Ternary)
@@ -634,7 +637,7 @@ namespace ChocolArm64.Instruction
                 }
 
                 EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
-                EmitVectorExtract(Context, Op.Rm, Elem,  Op.Size, Signed);
+                Context.EmitLdtmp();
 
                 Emit();
 
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