From 55374ebba0ed49bc4624e47cc971b1e63f644583 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Tue, 14 Aug 2018 23:54:12 -0300 Subject: Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273) --- ChocolArm64/Instruction/AInstEmitSimdHelper.cs | 34 ++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) (limited to 'ChocolArm64/Instruction/AInstEmitSimdHelper.cs') diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs index a9af3902..4ecfdae3 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs @@ -110,7 +110,17 @@ namespace ChocolArm64.Instruction } } - public static void EmitSseOrSse2CallF(AILEmitterCtx Context, string Name) + public static void EmitScalarSseOrSse2CallF(AILEmitterCtx Context, string Name) + { + EmitSseOrSse2CallF(Context, Name, true); + } + + public static void EmitVectorSseOrSse2CallF(AILEmitterCtx Context, string Name) + { + EmitSseOrSse2CallF(Context, Name, false); + } + + public static void EmitSseOrSse2CallF(AILEmitterCtx Context, string Name, bool Scalar) { AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; @@ -160,7 +170,18 @@ namespace ChocolArm64.Instruction Context.EmitStvec(Op.Rd); - if (Op.RegisterSize == ARegisterSize.SIMD64) + if (Scalar) + { + if (SizeF == 0) + { + EmitVectorZero32_128(Context, Op.Rd); + } + else /* if (SizeF == 1) */ + { + EmitVectorZeroUpper(Context, Op.Rd); + } + } + else if (Op.RegisterSize == ARegisterSize.SIMD64) { EmitVectorZeroUpper(Context, Op.Rd); } @@ -1238,6 +1259,15 @@ namespace ChocolArm64.Instruction EmitVectorInsert(Context, Rd, 1, 3, 0); } + public static void EmitVectorZero32_128(AILEmitterCtx Context, int Reg) + { + Context.EmitLdvec(Reg); + + AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorZero32_128)); + + Context.EmitStvec(Reg); + } + public static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size) { ThrowIfInvalid(Index, Size); -- cgit v1.2.3