From a0c78f792012cdea060444d7cb6a36dbabb04d52 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sat, 8 Sep 2018 19:24:29 +0200
Subject: Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)

* Update AOpCodeTable.cs

* Update AInstEmitSimdShift.cs

* Update ASoftFallback.cs

* Update AOpCodeSimdShImm.cs

* Update ABitUtils.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Create CpuTestSimdShImm.cs

* Create CpuTestSimdRegElem.cs

* Address PR feedback.

* Nit.

* Nit.
---
 ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs')

diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
index a291a7e5..b9aedd07 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
@@ -957,6 +957,15 @@ namespace ChocolArm64.Instruction
             });
         }
 
+        public static void Mls_Ve(AILEmitterCtx Context)
+        {
+            EmitVectorTernaryOpByElemZx(Context, () =>
+            {
+                Context.Emit(OpCodes.Mul);
+                Context.Emit(OpCodes.Sub);
+            });
+        }
+
         public static void Mul_V(AILEmitterCtx Context)
         {
             EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
-- 
cgit v1.2.3