From ad00fd02442cf9c0f00c4562635738042b521efa Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sun, 2 Dec 2018 01:34:43 +0100
Subject: Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516)

* Update OpCodeTable.cs

* Update InstEmitSimdShift.cs

* Update SoftFallback.cs

* Update CpuTestSimdReg.cs

* Nit.

* Update SoftFallback.cs

* Update Optimizations.cs

* Update InstEmitSimdLogical.cs

* Update InstEmitSimdArithmetic.cs
---
 ChocolArm64/Decoders/OpCodeSimdFcond64.cs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'ChocolArm64/Decoders')

diff --git a/ChocolArm64/Decoders/OpCodeSimdFcond64.cs b/ChocolArm64/Decoders/OpCodeSimdFcond64.cs
index b0f1c0eb..f805b3c1 100644
--- a/ChocolArm64/Decoders/OpCodeSimdFcond64.cs
+++ b/ChocolArm64/Decoders/OpCodeSimdFcond64.cs
@@ -10,8 +10,8 @@ namespace ChocolArm64.Decoders
 
         public OpCodeSimdFcond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
         {
-            Nzcv =         (opCode >>  0) & 0xf;
+            Nzcv =        (opCode >>  0) & 0xf;
             Cond = (Cond)((opCode >> 12) & 0xf);
         }
     }
-}
\ No newline at end of file
+}
-- 
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