From 9cb57fb4bb3bbae0ae052a5af4a96a49fc5d864d Mon Sep 17 00:00:00 2001
From: Alex Barney <thealexbarney@gmail.com>
Date: Tue, 30 Oct 2018 19:43:02 -0600
Subject: Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)

* Change naming convention for Ryujinx project

* Change naming convention for ChocolArm64 project

* Fix NaN

* Remove unneeded this. from Ryujinx project

* Adjust naming from new PRs

* Name changes based on feedback

* How did this get removed?

* Rebasing fix

* Change FP enum case

* Remove prefix from ChocolArm64 classes - Part 1

* Remove prefix from ChocolArm64 classes - Part 2

* Fix alignment from last commit's renaming

* Rename namespaces

* Rename stragglers

* Fix alignment

* Rename OpCode class

* Missed a few

* Adjust alignment
---
 ChocolArm64/Decoders/OpCodeSimdMemMs64.cs | 49 +++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 ChocolArm64/Decoders/OpCodeSimdMemMs64.cs

(limited to 'ChocolArm64/Decoders/OpCodeSimdMemMs64.cs')

diff --git a/ChocolArm64/Decoders/OpCodeSimdMemMs64.cs b/ChocolArm64/Decoders/OpCodeSimdMemMs64.cs
new file mode 100644
index 00000000..0748ef43
--- /dev/null
+++ b/ChocolArm64/Decoders/OpCodeSimdMemMs64.cs
@@ -0,0 +1,49 @@
+using ChocolArm64.Instructions;
+using ChocolArm64.State;
+
+namespace ChocolArm64.Decoders
+{
+    class OpCodeSimdMemMs64 : OpCodeMemReg64, IOpCodeSimd64
+    {
+        public int  Reps   { get; private set; }
+        public int  SElems { get; private set; }
+        public int  Elems  { get; private set; }
+        public bool WBack  { get; private set; }
+
+        public OpCodeSimdMemMs64(Inst inst, long position, int opCode) : base(inst, position, opCode)
+        {
+            switch ((opCode >> 12) & 0xf)
+            {
+                case 0b0000: Reps = 1; SElems = 4; break;
+                case 0b0010: Reps = 4; SElems = 1; break;
+                case 0b0100: Reps = 1; SElems = 3; break;
+                case 0b0110: Reps = 3; SElems = 1; break;
+                case 0b0111: Reps = 1; SElems = 1; break;
+                case 0b1000: Reps = 1; SElems = 2; break;
+                case 0b1010: Reps = 2; SElems = 1; break;
+
+                default: inst = Inst.Undefined; return;
+            }
+
+            Size  =  (opCode >> 10) & 3;
+            WBack = ((opCode >> 23) & 1) != 0;
+
+            bool q = ((opCode >> 30) & 1) != 0;
+
+            if (!q && Size == 3 && SElems != 1)
+            {
+                inst = Inst.Undefined;
+
+                return;
+            }
+
+            Extend64 = false;
+
+            RegisterSize = q
+                ? State.RegisterSize.Simd128
+                : State.RegisterSize.Simd64;
+
+            Elems = (GetBitsCount() >> 3) >> Size;
+        }
+    }
+}
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