From 36b9ab0e48b6893c057a954e1ef3181b452add1c Mon Sep 17 00:00:00 2001 From: gdkchan Date: Thu, 24 Jan 2019 23:59:53 -0200 Subject: Add ARM32 support on the translator (#561) * Remove ARM32 interpreter and add ARM32 support on the translator * Nits. * Rename Cond -> Condition * Align code again * Rename Data to Alu * Enable ARM32 support and handle undefined instructions * Use the IsThumb method to check if its a thumb opcode * Remove another 32-bits check --- ChocolArm64/Decoders/OpCodeBRegT16.cs | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 ChocolArm64/Decoders/OpCodeBRegT16.cs (limited to 'ChocolArm64/Decoders/OpCodeBRegT16.cs') diff --git a/ChocolArm64/Decoders/OpCodeBRegT16.cs b/ChocolArm64/Decoders/OpCodeBRegT16.cs new file mode 100644 index 00000000..c6c25130 --- /dev/null +++ b/ChocolArm64/Decoders/OpCodeBRegT16.cs @@ -0,0 +1,14 @@ +using ChocolArm64.Instructions; + +namespace ChocolArm64.Decoders +{ + class OpCodeBRegT16 : OpCodeT16, IOpCodeBReg32 + { + public int Rm { get; private set; } + + public OpCodeBRegT16(Inst inst, long position, int opCode) : base(inst, position, opCode) + { + Rm = (opCode >> 3) & 0xf; + } + } +} \ No newline at end of file -- cgit v1.2.3