From c1bdf19061ec679aa3c69eda2a41337e3e809014 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Tue, 29 Jan 2019 13:06:11 -0300 Subject: Implement some ARM32 memory instructions and CMP (#565) * Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table --- ChocolArm64/Decoders/IOpCodeBReg32.cs | 7 ------- 1 file changed, 7 deletions(-) delete mode 100644 ChocolArm64/Decoders/IOpCodeBReg32.cs (limited to 'ChocolArm64/Decoders/IOpCodeBReg32.cs') diff --git a/ChocolArm64/Decoders/IOpCodeBReg32.cs b/ChocolArm64/Decoders/IOpCodeBReg32.cs deleted file mode 100644 index fb9d94ea..00000000 --- a/ChocolArm64/Decoders/IOpCodeBReg32.cs +++ /dev/null @@ -1,7 +0,0 @@ -namespace ChocolArm64.Decoders -{ - interface IOpCodeBReg32 : IOpCode32 - { - int Rm { get; } - } -} \ No newline at end of file -- cgit v1.2.3