From 894459fcd7797b1e38f2448797d83856d11b6e23 Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Sun, 14 Oct 2018 04:35:16 +0200 Subject: Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449) * Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs * Update ASoftFallback.cs * Update ASoftFloat.cs * Update AOpCodeSimdRegElemF.cs * Update CpuTestSimdIns.cs * Update CpuTestSimdRegElem.cs * Create CpuTestSimdRegElemF.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Superseded Fmul_Se Test. Nit. * Address PR feedback. * Address PR feedback. * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update AInstEmitSimdShift.cs --- ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) (limited to 'ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs') diff --git a/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs b/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs index e61d7093..e0670def 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs +++ b/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs @@ -8,15 +8,26 @@ namespace ChocolArm64.Decoder public AOpCodeSimdRegElemF(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode) { - if ((Size & 1) != 0) + switch ((OpCode >> 21) & 3) // sz:L { - Index = (OpCode >> 11) & 1; - } - else - { - Index = (OpCode >> 21) & 1 | - (OpCode >> 10) & 2; + case 0: // H:0 + Index = (OpCode >> 10) & 2; // 0, 2 + + break; + + case 1: // H:1 + Index = (OpCode >> 10) & 2; + Index++; // 1, 3 + + break; + + case 2: // H + Index = (OpCode >> 11) & 1; // 0, 1 + + break; + + default: Emitter = AInstEmit.Und; return; } } } -} \ No newline at end of file +} -- cgit v1.2.3