From ab9d4b862d6ef5bc67cbb1afe0e1f55f24c028fa Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Wed, 23 Jun 2021 18:21:23 -0300
Subject: Implement VORN (register) Arm32 instruction (#2396)

---
 ARMeilleure/Decoders/OpCodeTable.cs               |  1 +
 ARMeilleure/Instructions/InstEmitSimdLogical32.cs | 18 ++++++++++++++++++
 ARMeilleure/Instructions/InstName.cs              |  1 +
 3 files changed, 20 insertions(+)

(limited to 'ARMeilleure')

diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs
index 028a5377..c1ac8363 100644
--- a/ARMeilleure/Decoders/OpCodeTable.cs
+++ b/ARMeilleure/Decoders/OpCodeTable.cs
@@ -907,6 +907,7 @@ namespace ARMeilleure.Decoders
             SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla,    InstEmit32.Vnmla_S,  OpCode32SimdRegS.Create);
             SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls,    InstEmit32.Vnmls_S,  OpCode32SimdRegS.Create);
             SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul,    InstEmit32.Vnmul_S,  OpCode32SimdRegS.Create);
+            SetA32("111100100x11xxxxxxxx0001xxx1xxxx", InstName.Vorn,     InstEmit32.Vorn_I,   OpCode32SimdBinary.Create);
             SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr,     InstEmit32.Vorr_I,   OpCode32SimdBinary.Create);
             SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr,     InstEmit32.Vorr_II,  OpCode32SimdImm.Create);
             SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd,    InstEmit32.Vpadd_I,  OpCode32SimdReg.Create);
diff --git a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
index 2d6bf481..48bf18bc 100644
--- a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
@@ -115,6 +115,24 @@ namespace ARMeilleure.Instructions
             }
         }
 
+        public static void Vorn_I(ArmEmitterContext context)
+        {
+            if (Optimizations.UseSse2)
+            {
+                Operand mask = context.VectorOne();
+
+                EmitVectorBinaryOpSimd32(context, (n, m) =>
+                {
+                    m = context.AddIntrinsic(Intrinsic.X86Pandn, m, mask);
+                    return context.AddIntrinsic(Intrinsic.X86Por, n, m);
+                });
+            }
+            else
+            {
+                EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseOr(op1, context.BitwiseNot(op2)));
+            }
+        }
+
         public static void Vorr_I(ArmEmitterContext context)
         {
             if (Optimizations.UseSse2)
diff --git a/ARMeilleure/Instructions/InstName.cs b/ARMeilleure/Instructions/InstName.cs
index fe7644a9..9b4e8961 100644
--- a/ARMeilleure/Instructions/InstName.cs
+++ b/ARMeilleure/Instructions/InstName.cs
@@ -605,6 +605,7 @@ namespace ARMeilleure.Instructions
         Vnmul,
         Vnmla,
         Vnmls,
+        Vorn,
         Vorr,
         Vpadd,
         Vpmax,
-- 
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