From 7b35ebc64a411e95e197bb36ad4b55c522c3703d Mon Sep 17 00:00:00 2001 From: merry Date: Tue, 22 Feb 2022 22:11:28 +0000 Subject: T32: Implement ALU (shifted register) instructions (#3135) * T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register) * OpCodeTable: Sort T32 list * Tests: Rename RandomTestCase to PrecomputedThumbTestCase * T32: Tests for AluRsImm instructions * fix nit * fix nit 2 --- ARMeilleure/Decoders/Decoder.cs | 5 +++++ ARMeilleure/Decoders/OpCodeT32.cs | 14 ++++++++++++++ ARMeilleure/Decoders/OpCodeT32Alu.cs | 20 +++++++++++++++++++ ARMeilleure/Decoders/OpCodeT32AluRsImm.cs | 20 +++++++++++++++++++ ARMeilleure/Decoders/OpCodeTable.cs | 31 ++++++++++++++++++++++++++---- ARMeilleure/Instructions/InstEmitAlu32.cs | 17 ++++++++++++++++ ARMeilleure/Instructions/InstEmitHelper.cs | 2 +- 7 files changed, 104 insertions(+), 5 deletions(-) create mode 100644 ARMeilleure/Decoders/OpCodeT32.cs create mode 100644 ARMeilleure/Decoders/OpCodeT32Alu.cs create mode 100644 ARMeilleure/Decoders/OpCodeT32AluRsImm.cs (limited to 'ARMeilleure') diff --git a/ARMeilleure/Decoders/Decoder.cs b/ARMeilleure/Decoders/Decoder.cs index e4839bf7..af3b0629 100644 --- a/ARMeilleure/Decoders/Decoder.cs +++ b/ARMeilleure/Decoders/Decoder.cs @@ -263,6 +263,11 @@ namespace ARMeilleure.Decoders // so we must consider such operations as a branch in potential aswell. if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc) { + if (opCode is OpCodeT32) + { + return opCode.Instruction.Name != InstName.Tst && opCode.Instruction.Name != InstName.Teq && + opCode.Instruction.Name != InstName.Cmp && opCode.Instruction.Name != InstName.Cmn; + } return true; } diff --git a/ARMeilleure/Decoders/OpCodeT32.cs b/ARMeilleure/Decoders/OpCodeT32.cs new file mode 100644 index 00000000..a3bd5c48 --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32.cs @@ -0,0 +1,14 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32 : OpCode32 + { + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32(inst, address, opCode); + + public OpCodeT32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Cond = Condition.Al; + + OpCodeSizeInBytes = 4; + } + } +} \ No newline at end of file diff --git a/ARMeilleure/Decoders/OpCodeT32Alu.cs b/ARMeilleure/Decoders/OpCodeT32Alu.cs new file mode 100644 index 00000000..a81b3b3d --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32Alu.cs @@ -0,0 +1,20 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32Alu : OpCodeT32, IOpCode32Alu + { + public int Rd { get; } + public int Rn { get; } + + public bool? SetFlags { get; } + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32Alu(inst, address, opCode); + + public OpCodeT32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rd = (opCode >> 8) & 0xf; + Rn = (opCode >> 16) & 0xf; + + SetFlags = ((opCode >> 20) & 1) != 0; + } + } +} \ No newline at end of file diff --git a/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs b/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs new file mode 100644 index 00000000..1c9ba7a2 --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs @@ -0,0 +1,20 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32AluRsImm : OpCodeT32Alu, IOpCode32AluRsImm + { + public int Rm { get; } + public int Immediate { get; } + + public ShiftType ShiftType { get; } + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluRsImm(inst, address, opCode); + + public OpCodeT32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rm = (opCode >> 0) & 0xf; + Immediate = ((opCode >> 6) & 3) | ((opCode >> 10) & 0x1c); + + ShiftType = (ShiftType)((opCode >> 4) & 3); + } + } +} \ No newline at end of file diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs index 1ea8885b..d290e554 100644 --- a/ARMeilleure/Decoders/OpCodeTable.cs +++ b/ARMeilleure/Decoders/OpCodeTable.cs @@ -1,6 +1,7 @@ using ARMeilleure.Instructions; using System; using System.Collections.Generic; +using System.Numerics; namespace ARMeilleure.Decoders { @@ -972,8 +973,7 @@ namespace ARMeilleure.Decoders SetA32("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip, InstEmit32.Vzip, OpCode32SimdCmpZ.Create); #endregion -#region "OpCode Table (AArch32, T16/T32)" - // T16 +#region "OpCode Table (AArch32, T16)" SetT16("000< makeOp(inst, address, (int)BitOperations.RotateRight((uint)opCode, 16)); + Set(reversedEncoding, AllInstT32, new InstDescriptor(name, emitter), reversedMakeOp); } private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) diff --git a/ARMeilleure/Instructions/InstEmitAlu32.cs b/ARMeilleure/Instructions/InstEmitAlu32.cs index 1cbc0765..a612bdf2 100644 --- a/ARMeilleure/Instructions/InstEmitAlu32.cs +++ b/ARMeilleure/Instructions/InstEmitAlu32.cs @@ -244,6 +244,23 @@ namespace ARMeilleure.Instructions EmitAluStore(context, res); } + public static void Orn(ArmEmitterContext context) + { + IOpCode32Alu op = (IOpCode32Alu)context.CurrOp; + + Operand n = GetAluN(context); + Operand m = GetAluM(context); + + Operand res = context.BitwiseOr(n, context.BitwiseNot(m)); + + if (ShouldSetFlags(context)) + { + EmitNZFlagsCheck(context, res); + } + + EmitAluStore(context, res); + } + public static void Pkh(ArmEmitterContext context) { OpCode32AluRsImm op = (OpCode32AluRsImm)context.CurrOp; diff --git a/ARMeilleure/Instructions/InstEmitHelper.cs b/ARMeilleure/Instructions/InstEmitHelper.cs index 433b0831..773f6bd6 100644 --- a/ARMeilleure/Instructions/InstEmitHelper.cs +++ b/ARMeilleure/Instructions/InstEmitHelper.cs @@ -12,7 +12,7 @@ namespace ARMeilleure.Instructions { public static bool IsThumb(OpCode op) { - return op is OpCodeT16; + return op is OpCodeT16 || op is OpCodeT32; } public static Operand GetExtendedM(ArmEmitterContext context, int rm, IntType type) -- cgit v1.2.3