From 3af2ce74ecf76cc8d6fdb9ff19101bfee47af7dd Mon Sep 17 00:00:00 2001 From: Valentin PONS Date: Sun, 19 Jul 2020 14:11:58 -0400 Subject: Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192) * Added some 32 bits instructions: * VBIC * VTST * VSRA * Incremented the PTC * Add tests and fix implementation * Fixed VBIC immediate opcode mapping * Hey hey! * Nit. Co-authored-by: gdkchan Co-authored-by: LDj3SNuD Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> --- ARMeilleure/Decoders/OpCodeTable.cs | 6 ++- ARMeilleure/Instructions/InstEmitSimdHelper32.cs | 31 ++++++++++- ARMeilleure/Instructions/InstEmitSimdLogical32.cs | 63 +++++++++++++++++++++-- ARMeilleure/Instructions/InstEmitSimdShift32.cs | 21 ++++++++ ARMeilleure/Instructions/InstName.cs | 3 ++ ARMeilleure/Translation/EmitterContext.cs | 5 ++ ARMeilleure/Translation/PTC/Ptc.cs | 2 +- 7 files changed, 125 insertions(+), 6 deletions(-) (limited to 'ARMeilleure') diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs index 66993bbb..bbcc15ba 100644 --- a/ARMeilleure/Decoders/OpCodeTable.cs +++ b/ARMeilleure/Decoders/OpCodeTable.cs @@ -806,6 +806,8 @@ namespace ARMeilleure.Decoders SetA32("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd, InstEmit32.Vadd_V, typeof(OpCode32SimdReg)); SetA32("1111001x1x<>>xxxxxxx0000>xx1xxxx", InstName.Vshr, InstEmit32.Vshr, typeof(OpCode32SimdShImm)); SetA32("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn, InstEmit32.Vshrn, typeof(OpCode32SimdShImmNarrow)); SetA32("<<<<11101x110001xxxx101x11x0xxxx", InstName.Vsqrt, InstEmit32.Vsqrt_S, typeof(OpCode32SimdS)); + SetA32("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra, InstEmit32.Vsra, typeof(OpCode32SimdShImm)); SetA32("111101001x00xxxxxxxx<<00xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, typeof(OpCode32SimdMemSingle)); SetA32("111101000x00xxxxxxxx0111xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, typeof(OpCode32SimdMemPair)); // Regs = 1. SetA32("111101000x00xxxxxxxx1010xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, typeof(OpCode32SimdMemPair)); // Regs = 2. @@ -952,6 +955,7 @@ namespace ARMeilleure.Decoders SetA32("1111001x1x<> op.Size; + + for (int index = 0; index < elems; index++) + { + Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size, signed); + Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed); + + res = EmitVectorInsert(context, res, emit(de, me), op.Id + index, op.Size); + } + + context.Copy(GetVecA32(op.Qd), res); + } + public static void EmitVectorTernaryLongOpI32(ArmEmitterContext context, Func3I emit, bool signed) { OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp; diff --git a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs index 6505e834..2d6bf481 100644 --- a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs @@ -15,7 +15,7 @@ namespace ARMeilleure.Instructions { if (Optimizations.UseSse2) { - EmitVectorBinaryOpF32(context, Intrinsic.X86Pand, Intrinsic.X86Pand); + EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Pand, n, m)); } else { @@ -23,6 +23,54 @@ namespace ARMeilleure.Instructions } } + public static void Vbic_I(ArmEmitterContext context) + { + if (Optimizations.UseSse2) + { + EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Pandn, m, n)); + } + else + { + EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseAnd(op1, context.BitwiseNot(op2))); + } + } + + public static void Vbic_II(ArmEmitterContext context) + { + OpCode32SimdImm op = (OpCode32SimdImm)context.CurrOp; + + long immediate = op.Immediate; + + // Replicate fields to fill the 64-bits, if size is < 64-bits. + switch (op.Size) + { + case 0: immediate *= 0x0101010101010101L; break; + case 1: immediate *= 0x0001000100010001L; break; + case 2: immediate *= 0x0000000100000001L; break; + } + + Operand imm = Const(immediate); + Operand res = GetVecA32(op.Qd); + + if (op.Q) + { + for (int elem = 0; elem < 2; elem++) + { + Operand de = EmitVectorExtractZx(context, op.Qd, elem, 3); + + res = EmitVectorInsert(context, res, context.BitwiseAnd(de, context.BitwiseNot(imm)), elem, 3); + } + } + else + { + Operand de = EmitVectorExtractZx(context, op.Qd, op.Vd & 1, 3); + + res = EmitVectorInsert(context, res, context.BitwiseAnd(de, context.BitwiseNot(imm)), op.Vd & 1, 3); + } + + context.Copy(GetVecA32(op.Qd), res); + } + public static void Vbif(ArmEmitterContext context) { EmitBifBit(context, true); @@ -59,7 +107,7 @@ namespace ARMeilleure.Instructions { if (Optimizations.UseSse2) { - EmitVectorBinaryOpF32(context, Intrinsic.X86Pxor, Intrinsic.X86Pxor); + EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Pxor, n, m)); } else { @@ -71,7 +119,7 @@ namespace ARMeilleure.Instructions { if (Optimizations.UseSse2) { - EmitVectorBinaryOpF32(context, Intrinsic.X86Por, Intrinsic.X86Por); + EmitVectorBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(Intrinsic.X86Por, n, m)); } else { @@ -115,6 +163,15 @@ namespace ARMeilleure.Instructions context.Copy(GetVecA32(op.Qd), res); } + public static void Vtst(ArmEmitterContext context) + { + EmitVectorBinaryOpZx32(context, (op1, op2) => + { + Operand isZero = context.ICompareEqual(context.BitwiseAnd(op1, op2), Const(0)); + return context.ConditionalSelect(isZero, Const(0), Const(-1)); + }); + } + private static void EmitBifBit(ArmEmitterContext context, bool notRm) { OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp; diff --git a/ARMeilleure/Instructions/InstEmitSimdShift32.cs b/ARMeilleure/Instructions/InstEmitSimdShift32.cs index b9055c30..215fe1e8 100644 --- a/ARMeilleure/Instructions/InstEmitSimdShift32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdShift32.cs @@ -129,6 +129,27 @@ namespace ARMeilleure.Instructions EmitVectorUnaryNarrowOp32(context, (op1) => context.ShiftRightUI(op1, Const(shift))); } + public static void Vsra(ArmEmitterContext context) + { + OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp; + int shift = GetImmShr(op); + int maxShift = (8 << op.Size) - 1; + + if (op.U) + { + EmitVectorImmBinaryQdQmOpZx32(context, (op1, op2) => + { + Operand shiftRes = shift > maxShift ? Const(op2.Type, 0) : context.ShiftRightUI(op2, Const(shift)); + + return context.Add(op1, shiftRes); + }); + } + else + { + EmitVectorImmBinaryQdQmOpSx32(context, (op1, op2) => context.Add(op1, context.ShiftRightSI(op2, Const(Math.Min(maxShift, shift))))); + } + } + private static Operand EmitShlRegOp(ArmEmitterContext context, Operand op, Operand shiftLsB, int size, bool unsigned) { if (shiftLsB.Type == OperandType.I64) diff --git a/ARMeilleure/Instructions/InstName.cs b/ARMeilleure/Instructions/InstName.cs index 28041874..d7283029 100644 --- a/ARMeilleure/Instructions/InstName.cs +++ b/ARMeilleure/Instructions/InstName.cs @@ -547,6 +547,7 @@ namespace ARMeilleure.Instructions Vadd, Vaddw, Vand, + Vbic, Vbif, Vbit, Vbsl, @@ -611,10 +612,12 @@ namespace ARMeilleure.Instructions Vrecps, Vrsqrte, Vrsqrts, + Vsra, Vsub, Vsubw, Vtbl, Vtrn, + Vtst, Vuzp, Vzip, } diff --git a/ARMeilleure/Translation/EmitterContext.cs b/ARMeilleure/Translation/EmitterContext.cs index 656f1704..74421854 100644 --- a/ARMeilleure/Translation/EmitterContext.cs +++ b/ARMeilleure/Translation/EmitterContext.cs @@ -441,6 +441,11 @@ namespace ARMeilleure.Translation return Add(Instruction.VectorInsert8, Local(OperandType.V128), vector, value, Const(index)); } + public Operand VectorOne() + { + return Add(Instruction.VectorOne, Local(OperandType.V128)); + } + public Operand VectorZero() { return Add(Instruction.VectorZero, Local(OperandType.V128)); diff --git a/ARMeilleure/Translation/PTC/Ptc.cs b/ARMeilleure/Translation/PTC/Ptc.cs index 9db7c162..032e111e 100644 --- a/ARMeilleure/Translation/PTC/Ptc.cs +++ b/ARMeilleure/Translation/PTC/Ptc.cs @@ -20,7 +20,7 @@ namespace ARMeilleure.Translation.PTC { private const string HeaderMagic = "PTChd"; - private const int InternalVersion = 12; //! To be incremented manually for each change to the ARMeilleure project. + private const int InternalVersion = 13; //! To be incremented manually for each change to the ARMeilleure project. private const string BaseDir = "Ryujinx"; -- cgit v1.2.3