From f0824fde9f511e9f6d1cda1f80549c93a5d6ce69 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Fri, 21 Jan 2022 12:47:34 -0300 Subject: Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) * Add host CPU memory barriers for DMB/DSB and ordered load/store * PPTC version bump * Revert to old barrier order --- ARMeilleure/Translation/PTC/Ptc.cs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ARMeilleure/Translation/PTC') diff --git a/ARMeilleure/Translation/PTC/Ptc.cs b/ARMeilleure/Translation/PTC/Ptc.cs index 2142e34f..4cf01a76 100644 --- a/ARMeilleure/Translation/PTC/Ptc.cs +++ b/ARMeilleure/Translation/PTC/Ptc.cs @@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC private const string OuterHeaderMagicString = "PTCohd\0\0"; private const string InnerHeaderMagicString = "PTCihd\0\0"; - private const uint InternalVersion = 2953; //! To be incremented manually for each change to the ARMeilleure project. + private const uint InternalVersion = 3015; //! To be incremented manually for each change to the ARMeilleure project. private const string ActualDir = "0"; private const string BackupDir = "1"; -- cgit v1.2.3