From f0824fde9f511e9f6d1cda1f80549c93a5d6ce69 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Fri, 21 Jan 2022 12:47:34 -0300
Subject: Add host CPU memory barriers for DMB/DSB and ordered load/store
 (#3015)

* Add host CPU memory barriers for DMB/DSB and ordered load/store

* PPTC version bump

* Revert to old barrier order
---
 ARMeilleure/Translation/EmitterContext.cs | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'ARMeilleure/Translation/EmitterContext.cs')

diff --git a/ARMeilleure/Translation/EmitterContext.cs b/ARMeilleure/Translation/EmitterContext.cs
index 7525a5d4..8fcb4dee 100644
--- a/ARMeilleure/Translation/EmitterContext.cs
+++ b/ARMeilleure/Translation/EmitterContext.cs
@@ -325,6 +325,11 @@ namespace ARMeilleure.Translation
             Add(Instruction.LoadFromContext);
         }
 
+        public void MemoryBarrier()
+        {
+            Add(Instruction.MemoryBarrier);
+        }
+
         public Operand Multiply(Operand op1, Operand op2)
         {
             return Add(Instruction.Multiply, Local(op1.Type), op1, op2);
-- 
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