From 430ba6da65a781196db7d723cc88710bb7f5caf8 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Mon, 4 Jan 2021 23:45:54 +0100
Subject: CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D ->
 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and
 "1/2D -> 1Q" variants; with Test. (#1817)

* Add Pmull_V Sse fast path only, both "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test.

* Add Clmul fast path for the 128 bits variant.

* Small optimisation (save 60 instructions) for the Sse fast path about the 128 bits variant.

* Add slow path, both variants. Fix V128 Shl/Shr when shift = 0.

* A32: Add Vmull_I P64 variant (slow path); not tested.

* A32: Add Vmull_I_P8_P64 Test and fix P64 variant.
---
 ARMeilleure/State/V128.cs | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'ARMeilleure/State')

diff --git a/ARMeilleure/State/V128.cs b/ARMeilleure/State/V128.cs
index 399cea13..3fa9f9a9 100644
--- a/ARMeilleure/State/V128.cs
+++ b/ARMeilleure/State/V128.cs
@@ -189,6 +189,11 @@ namespace ARMeilleure.State
         /// </remarks>
         public static V128 operator <<(V128 x, int shift)
         {
+            if (shift == 0)
+            {
+                return new V128(x._e0, x._e1);
+            }
+
             ulong shiftOut = x._e0 >> (64 - shift);
 
             return new V128(x._e0 << shift, (x._e1 << shift) | shiftOut);
@@ -205,6 +210,11 @@ namespace ARMeilleure.State
         /// </remarks>
         public static V128 operator >>(V128 x, int shift)
         {
+            if (shift == 0)
+            {
+                return new V128(x._e0, x._e1);
+            }
+
             ulong shiftOut = x._e1 & ((1UL << shift) - 1);
 
             return new V128((x._e0 >> shift) | (shiftOut << (64 - shift)), x._e1 >> shift);
-- 
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