From f0824fde9f511e9f6d1cda1f80549c93a5d6ce69 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Fri, 21 Jan 2022 12:47:34 -0300
Subject: Add host CPU memory barriers for DMB/DSB and ordered load/store
 (#3015)

* Add host CPU memory barriers for DMB/DSB and ordered load/store

* PPTC version bump

* Revert to old barrier order
---
 ARMeilleure/Instructions/InstEmitMemoryEx.cs | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'ARMeilleure/Instructions')

diff --git a/ARMeilleure/Instructions/InstEmitMemoryEx.cs b/ARMeilleure/Instructions/InstEmitMemoryEx.cs
index 522b2a47..88b9d2f0 100644
--- a/ARMeilleure/Instructions/InstEmitMemoryEx.cs
+++ b/ARMeilleure/Instructions/InstEmitMemoryEx.cs
@@ -167,9 +167,7 @@ namespace ARMeilleure.Instructions
 
         private static void EmitBarrier(ArmEmitterContext context)
         {
-            // Note: This barrier is most likely not necessary, and probably
-            // doesn't make any difference since we need to do a ton of stuff
-            // (software MMU emulation) to read or write anything anyway.
+            context.MemoryBarrier();
         }
     }
 }
\ No newline at end of file
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