From 7b35ebc64a411e95e197bb36ad4b55c522c3703d Mon Sep 17 00:00:00 2001 From: merry Date: Tue, 22 Feb 2022 22:11:28 +0000 Subject: T32: Implement ALU (shifted register) instructions (#3135) * T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register) * OpCodeTable: Sort T32 list * Tests: Rename RandomTestCase to PrecomputedThumbTestCase * T32: Tests for AluRsImm instructions * fix nit * fix nit 2 --- ARMeilleure/Instructions/InstEmitAlu32.cs | 17 +++++++++++++++++ ARMeilleure/Instructions/InstEmitHelper.cs | 2 +- 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'ARMeilleure/Instructions') diff --git a/ARMeilleure/Instructions/InstEmitAlu32.cs b/ARMeilleure/Instructions/InstEmitAlu32.cs index 1cbc0765..a612bdf2 100644 --- a/ARMeilleure/Instructions/InstEmitAlu32.cs +++ b/ARMeilleure/Instructions/InstEmitAlu32.cs @@ -244,6 +244,23 @@ namespace ARMeilleure.Instructions EmitAluStore(context, res); } + public static void Orn(ArmEmitterContext context) + { + IOpCode32Alu op = (IOpCode32Alu)context.CurrOp; + + Operand n = GetAluN(context); + Operand m = GetAluM(context); + + Operand res = context.BitwiseOr(n, context.BitwiseNot(m)); + + if (ShouldSetFlags(context)) + { + EmitNZFlagsCheck(context, res); + } + + EmitAluStore(context, res); + } + public static void Pkh(ArmEmitterContext context) { OpCode32AluRsImm op = (OpCode32AluRsImm)context.CurrOp; diff --git a/ARMeilleure/Instructions/InstEmitHelper.cs b/ARMeilleure/Instructions/InstEmitHelper.cs index 433b0831..773f6bd6 100644 --- a/ARMeilleure/Instructions/InstEmitHelper.cs +++ b/ARMeilleure/Instructions/InstEmitHelper.cs @@ -12,7 +12,7 @@ namespace ARMeilleure.Instructions { public static bool IsThumb(OpCode op) { - return op is OpCodeT16; + return op is OpCodeT16 || op is OpCodeT32; } public static Operand GetExtendedM(ArmEmitterContext context, int rm, IntType type) -- cgit v1.2.3