From 56a61a57582e0fa7951bdb3d96b343ac01063e1f Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Fri, 17 Jul 2020 15:57:49 +0200 Subject: CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394) * Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. * Update Ptc.cs --- ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'ARMeilleure/Instructions') diff --git a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs index cc6e6edb..f7f3d47e 100644 --- a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs @@ -33,7 +33,7 @@ namespace ARMeilleure.Instructions public static void Vabs_V(ArmEmitterContext context) { - OpCode32Simd op = (OpCode32Simd)context.CurrOp; + OpCode32SimdCmpZ op = (OpCode32SimdCmpZ)context.CurrOp; if (op.F) { @@ -385,22 +385,22 @@ namespace ARMeilleure.Instructions public static void Vneg_V(ArmEmitterContext context) { - OpCode32Simd op = (OpCode32Simd)context.CurrOp; + OpCode32SimdCmpZ op = (OpCode32SimdCmpZ)context.CurrOp; if (op.F) { - if (Optimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse2) { EmitVectorUnaryOpSimd32(context, (m) => { if ((op.Size & 1) == 0) { - Operand mask = X86GetScalar(context, -0f); + Operand mask = X86GetAllElements(context, -0f); return context.AddIntrinsic(Intrinsic.X86Xorps, mask, m); } else { - Operand mask = X86GetScalar(context, -0d); + Operand mask = X86GetAllElements(context, -0d); return context.AddIntrinsic(Intrinsic.X86Xorpd, mask, m); } }); -- cgit v1.2.3