From 92d166ecb7e5b29a27bffd77754d8e592435ee6b Mon Sep 17 00:00:00 2001 From: gdkchan Date: Thu, 17 Feb 2022 22:53:18 -0300 Subject: Enable CPU JIT cache invalidation (#2965) * Enable CPU JIT cache invalidation * Invalidate cache on IC IVAU --- ARMeilleure/Instructions/InstEmitSystem.cs | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'ARMeilleure/Instructions/InstEmitSystem.cs') diff --git a/ARMeilleure/Instructions/InstEmitSystem.cs b/ARMeilleure/Instructions/InstEmitSystem.cs index 60c71f96..499f1648 100644 --- a/ARMeilleure/Instructions/InstEmitSystem.cs +++ b/ARMeilleure/Instructions/InstEmitSystem.cs @@ -12,7 +12,8 @@ namespace ARMeilleure.Instructions { static partial class InstEmit { - private const int DczSizeLog2 = 4; + private const int DczSizeLog2 = 4; // Log2 size in words + public const int DczSizeInBytes = 4 << DczSizeLog2; public static void Hint(ArmEmitterContext context) { @@ -87,7 +88,7 @@ namespace ARMeilleure.Instructions // DC ZVA Operand t = GetIntOrZR(context, op.Rt); - for (long offset = 0; offset < (4 << DczSizeLog2); offset += 8) + for (long offset = 0; offset < DczSizeInBytes; offset += 8) { Operand address = context.Add(t, Const(offset)); @@ -98,7 +99,12 @@ namespace ARMeilleure.Instructions } // No-op - case 0b11_011_0111_1110_001: //DC CIVAC + case 0b11_011_0111_1110_001: // DC CIVAC + break; + + case 0b11_011_0111_0101_001: // IC IVAU + Operand target = Register(op.Rt, RegisterType.Integer, OperandType.I64); + context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.InvalidateCacheLine)), target); break; } } -- cgit v1.2.3