From e24949ca2c7051586f6518ef524c93db0d4827c2 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Sun, 19 Dec 2021 11:19:05 -0300 Subject: Implement CSDB instruction (#2927) --- ARMeilleure/Instructions/InstEmitSimdMemory32.cs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'ARMeilleure/Instructions/InstEmitSimdMemory32.cs') diff --git a/ARMeilleure/Instructions/InstEmitSimdMemory32.cs b/ARMeilleure/Instructions/InstEmitSimdMemory32.cs index 1e8f7ccd..72474ee3 100644 --- a/ARMeilleure/Instructions/InstEmitSimdMemory32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdMemory32.cs @@ -99,7 +99,7 @@ namespace ARMeilleure.Instructions EmitLoadSimd(context, address, GetVecA32(dreg >> 1), dreg >> 1, rIndex++, op.Size); } } - } + } else { EmitLoadSimd(context, address, GetVecA32(d >> 1), d >> 1, index, op.Size); @@ -120,13 +120,13 @@ namespace ARMeilleure.Instructions { Operand m = GetIntA32(context, op.Rm); SetIntA32(context, op.Rn, context.Add(n, m)); - } + } else { SetIntA32(context, op.Rn, context.Add(n, Const(count * eBytes))); } } - } + } else { OpCode32SimdMemPair op = (OpCode32SimdMemPair)context.CurrOp; @@ -161,7 +161,7 @@ namespace ARMeilleure.Instructions } else { - + if (load) { EmitLoadSimd(context, address, GetVecA32(elemD >> 1), elemD >> 1, index, op.Size); @@ -213,7 +213,7 @@ namespace ARMeilleure.Instructions int sReg = (op.DoubleWidth) ? (op.Vd << 1) : op.Vd; int offset = 0; int byteSize = 4; - + for (int num = 0; num < range; num++, sReg++) { Operand address = context.Add(baseAddress, Const(offset)); -- cgit v1.2.3