From 89ccec197ec9a5db2bb308ef3e9178910d1ab7a8 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Tue, 10 Mar 2020 02:17:30 -0300 Subject: Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960) * Implement VMOVL and VORR.I32 AArch32 SIMD instructions * Rename
to on test description * Rename Widen to Long and improve VMOVL implementation a bit --- ARMeilleure/Instructions/InstEmitSimdLogical32.cs | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'ARMeilleure/Instructions/InstEmitSimdLogical32.cs') diff --git a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs index fef40a17..3698f332 100644 --- a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs @@ -2,7 +2,10 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; +using static ARMeilleure.Instructions.InstEmitHelper; +using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper32; +using static ARMeilleure.IntermediateRepresentation.OperandHelper; namespace ARMeilleure.Instructions { @@ -64,6 +67,42 @@ namespace ARMeilleure.Instructions } } + public static void Vorr_II(ArmEmitterContext context) + { + OpCode32SimdImm op = (OpCode32SimdImm)context.CurrOp; + + long immediate = op.Immediate; + + // Replicate fields to fill the 64-bits, if size is < 64-bits. + switch (op.Size) + { + case 0: immediate *= 0x0101010101010101L; break; + case 1: immediate *= 0x0001000100010001L; break; + case 2: immediate *= 0x0000000100000001L; break; + } + + Operand imm = Const(immediate); + Operand res = GetVecA32(op.Qd); + + if (op.Q) + { + for (int elem = 0; elem < 2; elem++) + { + Operand de = EmitVectorExtractZx(context, op.Qd, elem, 3); + + res = EmitVectorInsert(context, res, context.BitwiseOr(de, imm), elem, 3); + } + } + else + { + Operand de = EmitVectorExtractZx(context, op.Qd, op.Vd & 1, 3); + + res = EmitVectorInsert(context, res, context.BitwiseOr(de, imm), op.Vd & 1, 3); + } + + context.Copy(GetVecA32(op.Qd), res); + } + private static void EmitBifBit(ArmEmitterContext context, bool notRm) { OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp; -- cgit v1.2.3