From e36e97c64d7b973fbbc3ac92e9f115d74a4d9e2d Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sat, 8 Aug 2020 17:18:51 +0200
Subject: CPU: This PR fixes Fpscr, among other things. (#1433)

* CPU: This PR fixes Fpscr, among other things.

* Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.

* Fix Vcmp & Vcmpe opcode table.

* Revert "Fix Vcmp & Vcmpe opcode table."

This reverts commit c117d9410d693185ff5f8ee8e457ffbfb2027dd5.

* Address PR feedbacks.
---
 ARMeilleure/Instructions/InstEmitSimdCmp32.cs | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

(limited to 'ARMeilleure/Instructions/InstEmitSimdCmp32.cs')

diff --git a/ARMeilleure/Instructions/InstEmitSimdCmp32.cs b/ARMeilleure/Instructions/InstEmitSimdCmp32.cs
index db925053..290cc17e 100644
--- a/ARMeilleure/Instructions/InstEmitSimdCmp32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdCmp32.cs
@@ -307,7 +307,10 @@ namespace ARMeilleure.Instructions
                     Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisseq, n, m);
                     Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisslt, n, m);
 
-                    EmitSetFPSCRFlags(context, nf, zf, cf, Const(0));
+                    SetFpFlag(context, FPState.VFlag, Const(0));
+                    SetFpFlag(context, FPState.CFlag, cf);
+                    SetFpFlag(context, FPState.ZFlag, zf);
+                    SetFpFlag(context, FPState.NFlag, nf);
                 }
                 else
                 {
@@ -321,14 +324,20 @@ namespace ARMeilleure.Instructions
                     Operand zf = context.AddIntrinsicInt(Intrinsic.X86Comisdeq, n, m);
                     Operand nf = context.AddIntrinsicInt(Intrinsic.X86Comisdlt, n, m);
 
-                    EmitSetFPSCRFlags(context, nf, zf, cf, Const(0));
+                    SetFpFlag(context, FPState.VFlag, Const(0));
+                    SetFpFlag(context, FPState.CFlag, cf);
+                    SetFpFlag(context, FPState.ZFlag, zf);
+                    SetFpFlag(context, FPState.NFlag, nf);
                 }
 
                 context.Branch(lblEnd);
 
                 context.MarkLabel(lblNaN);
 
-                EmitSetFPSCRFlags(context, Const(3));
+                SetFpFlag(context, FPState.VFlag, Const(1));
+                SetFpFlag(context, FPState.CFlag, Const(1));
+                SetFpFlag(context, FPState.ZFlag, Const(0));
+                SetFpFlag(context, FPState.NFlag, Const(0));
 
                 context.MarkLabel(lblEnd);
             }
@@ -354,11 +363,11 @@ namespace ARMeilleure.Instructions
 
                 Operand nzcv = context.Call(info, ne, me, Const(signalNaNs));
 
-                EmitSetFPSCRFlags(context, nzcv);
+                EmitSetFpscrNzcv(context, nzcv);
             }
         }
 
-        private static void EmitSetFPSCRFlags(ArmEmitterContext context, Operand nzcv)
+        private static void EmitSetFpscrNzcv(ArmEmitterContext context, Operand nzcv)
         {
             Operand Extract(Operand value, int bit)
             {
@@ -378,14 +387,6 @@ namespace ARMeilleure.Instructions
             SetFpFlag(context, FPState.NFlag, Extract(nzcv, 3));
         }
 
-        private static void EmitSetFPSCRFlags(ArmEmitterContext context, Operand n, Operand z, Operand c, Operand v)
-        {
-            SetFpFlag(context, FPState.VFlag, v);
-            SetFpFlag(context, FPState.CFlag, c);
-            SetFpFlag(context, FPState.ZFlag, z);
-            SetFpFlag(context, FPState.NFlag, n);
-        }
-
         private static void EmitSse2OrAvxCmpOpF32(ArmEmitterContext context, CmpCondition cond, bool zero)
         {
             OpCode32Simd op = (OpCode32Simd)context.CurrOp;
-- 
cgit v1.2.3