From 9878fc2d3cf4c64f56c44c2a5de013acb6bcbade Mon Sep 17 00:00:00 2001 From: gdkchan Date: Thu, 30 Jul 2020 11:29:28 -0300 Subject: Implement inline memory load/store exclusive and ordered (#1413) * Implement inline memory load/store exclusive * Fix missing REX prefix on 8-bits CMPXCHG * Increment PTC version due to bugfix * Remove redundant memory checks * Address PR feedback * Increment PPTC version --- ARMeilleure/Instructions/InstEmitMemoryEx.cs | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) (limited to 'ARMeilleure/Instructions/InstEmitMemoryEx.cs') diff --git a/ARMeilleure/Instructions/InstEmitMemoryEx.cs b/ARMeilleure/Instructions/InstEmitMemoryEx.cs index 7ca019de..977f23d3 100644 --- a/ARMeilleure/Instructions/InstEmitMemoryEx.cs +++ b/ARMeilleure/Instructions/InstEmitMemoryEx.cs @@ -23,7 +23,7 @@ namespace ARMeilleure.Instructions public static void Clrex(ArmEmitterContext context) { - context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ClearExclusive))); + EmitClearExclusive(context); } public static void Dmb(ArmEmitterContext context) => EmitBarrier(context); @@ -139,8 +139,6 @@ namespace ARMeilleure.Instructions Operand t = GetIntOrZR(context, op.Rt); - Operand s = null; - if (pair) { Debug.Assert(op.Size == 2 || op.Size == 3, "Invalid size for pairwise store."); @@ -159,18 +157,11 @@ namespace ARMeilleure.Instructions value = context.VectorInsert(value, t2, 1); } - s = EmitStoreExclusive(context, address, value, exclusive, op.Size + 1); + EmitStoreExclusive(context, address, value, exclusive, op.Size + 1, op.Rs, a32: false); } else { - s = EmitStoreExclusive(context, address, t, exclusive, op.Size); - } - - if (s != null) - { - // This is only needed for exclusive stores. The function returns 0 - // when the store is successful, and 1 otherwise. - SetIntOrZR(context, op.Rs, s); + EmitStoreExclusive(context, address, t, exclusive, op.Size, op.Rs, a32: false); } } -- cgit v1.2.3