From fb0939f9b68d7fb83d863b22ef99af93452bb4bf Mon Sep 17 00:00:00 2001 From: gdkchan Date: Sat, 29 Feb 2020 17:51:55 -0300 Subject: Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954) * Implement SMULWB, SMULWT, SMLAWB, SMLAWT, and add tests for some multiply instructions * Improve test descriptions * Rename SMULH to SMUL__ * Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions * Fix new tests * Replace AND 0xFFFF with 16-bits zero extension (more efficient) --- ARMeilleure/Instructions/InstEmitAluHelper.cs | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'ARMeilleure/Instructions/InstEmitAluHelper.cs') diff --git a/ARMeilleure/Instructions/InstEmitAluHelper.cs b/ARMeilleure/Instructions/InstEmitAluHelper.cs index 3bb87f27..916a1da5 100644 --- a/ARMeilleure/Instructions/InstEmitAluHelper.cs +++ b/ARMeilleure/Instructions/InstEmitAluHelper.cs @@ -297,6 +297,21 @@ namespace ARMeilleure.Instructions return m; } + public static int DecodeImmShift(ShiftType shiftType, int shift) + { + if (shift == 0) + { + switch (shiftType) + { + case ShiftType.Lsr: shift = 32; break; + case ShiftType.Asr: shift = 32; break; + case ShiftType.Ror: shift = 1; break; + } + } + + return shift; + } + public static Operand GetMShiftedByReg(ArmEmitterContext context, OpCode32AluRsReg op, bool setCarry) { Operand m = GetIntA32(context, op.Rm); @@ -328,7 +343,7 @@ namespace ARMeilleure.Instructions if (expected) { context.BranchIfFalse(endLabel, boolValue); - } + } else { context.BranchIfTrue(endLabel, boolValue); @@ -411,7 +426,7 @@ namespace ARMeilleure.Instructions SetFlag(context, PState.CFlag, cOut); }, false); } - + return context.ConditionalSelect(shiftLarge, Const(0), result); } -- cgit v1.2.3