From eba682b767a60db51ff624ae48a3ca0124634705 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Thu, 25 Aug 2022 06:59:34 -0300 Subject: Implement some 32-bit Thumb instructions (#3614) * Implement some 32-bit Thumb instructions * Optimize OpCode32MemMult using PopCount --- ARMeilleure/Decoders/OpCodeT32MemRsImm.cs | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 ARMeilleure/Decoders/OpCodeT32MemRsImm.cs (limited to 'ARMeilleure/Decoders/OpCodeT32MemRsImm.cs') diff --git a/ARMeilleure/Decoders/OpCodeT32MemRsImm.cs b/ARMeilleure/Decoders/OpCodeT32MemRsImm.cs new file mode 100644 index 00000000..056d3b46 --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32MemRsImm.cs @@ -0,0 +1,30 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32MemRsImm : OpCodeT32, IOpCode32MemRsImm + { + public int Rt { get; } + public int Rn { get; } + public int Rm { get; } + public ShiftType ShiftType => ShiftType.Lsl; + + public bool WBack => false; + public bool IsLoad { get; } + public bool Index => true; + public bool Add => true; + + public int Immediate { get; } + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MemRsImm(inst, address, opCode); + + public OpCodeT32MemRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rm = (opCode >> 0) & 0xf; + Rt = (opCode >> 12) & 0xf; + Rn = (opCode >> 16) & 0xf; + + IsLoad = (opCode & (1 << 20)) != 0; + + Immediate = (opCode >> 4) & 3; + } + } +} -- cgit v1.2.3