From 04e330cc004add7550eef8361cd490fac99255e2 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Tue, 13 Oct 2020 22:41:33 +0200
Subject: Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s
 (slow paths). (#1577)

* Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths).

No test provided (i.e. draft).

* Ptc InternalVersion = 1577
---
 ARMeilleure/Decoders/OpCode32SimdShImmLong.cs | 40 +++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 ARMeilleure/Decoders/OpCode32SimdShImmLong.cs

(limited to 'ARMeilleure/Decoders/OpCode32SimdShImmLong.cs')

diff --git a/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs b/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
new file mode 100644
index 00000000..1e77b950
--- /dev/null
+++ b/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
@@ -0,0 +1,40 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCode32SimdShImmLong : OpCode32Simd
+    {
+        public int Shift { get; private set; }
+
+        public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Q = false;
+            RegisterSize = RegisterSize.Simd64;
+
+            int imm6 = (opCode >> 16) & 0x3f;
+
+            if ((imm6 & 0x20) == 0b100000)
+            {
+                Size = 2;
+                Shift = imm6 - 32;
+            }
+            else if ((imm6 & 0x30) == 0b010000)
+            {
+                Size = 1;
+                Shift = imm6 - 16;
+            }
+            else if ((imm6 & 0x38) == 0b001000)
+            {
+                Size = 0;
+                Shift = imm6 - 8;
+            }
+            else
+            {
+                Instruction = InstDescriptor.Undefined;
+            }
+
+            if (GetType() == typeof(OpCode32SimdShImmLong) && DecoderHelper.VectorArgumentsInvalid(true, Vd))
+            {
+                Instruction = InstDescriptor.Undefined;
+            }
+        }
+    }
+}
-- 
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