From 04e330cc004add7550eef8361cd490fac99255e2 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Tue, 13 Oct 2020 22:41:33 +0200
Subject: Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s
 (slow paths). (#1577)

* Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths).

No test provided (i.e. draft).

* Ptc InternalVersion = 1577
---
 ARMeilleure/Decoders/OpCode32SimdRegLong.cs | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'ARMeilleure/Decoders/OpCode32SimdRegLong.cs')

diff --git a/ARMeilleure/Decoders/OpCode32SimdRegLong.cs b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
index 24ae42d8..144824b3 100644
--- a/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
@@ -8,7 +8,14 @@
         {
             Q = false;
             RegisterSize = RegisterSize.Simd64;
+
             Polynomial = ((opCode >> 9) & 0x1) != 0;
+
+            // Subclasses have their own handling of Vx to account for before checking.
+            if (GetType() == typeof(OpCode32SimdRegLong) && DecoderHelper.VectorArgumentsInvalid(true, Vd))
+            {
+                Instruction = InstDescriptor.Undefined;
+            }
         }
     }
 }
-- 
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