From c26f3774bdbf3982149a3ea4c0f7abb4de869db7 Mon Sep 17 00:00:00 2001
From: gdkchan <gab.dark.100@gmail.com>
Date: Tue, 10 Mar 2020 21:49:27 -0300
Subject: Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions
 + other fixes (#977)

* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes

* Re-align opcode table

* Re-enable undefined, use subclasses to fix checks

* Add test and fix VRSHR instruction

* PR feedback
---
 ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs

(limited to 'ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs')

diff --git a/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs b/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
new file mode 100644
index 00000000..26f86f34
--- /dev/null
+++ b/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
@@ -0,0 +1,19 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCode32SimdRegElemLong : OpCode32SimdRegElem
+    {
+        public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Q = false;
+            F = false;
+
+            RegisterSize = RegisterSize.Simd64;
+
+            // (Vd & 1) != 0 || Size == 3 are also invalid, but they are checked on encoding.
+            if (Size == 0)
+            {
+                Instruction = InstDescriptor.Undefined;
+            }
+        }
+    }
+}
-- 
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