Ryujinx - A backup of the Ryujinx master git branch.

Age	Commit message (Collapse)	Author
2018-09-26	Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT ↵	gdkchan
	(Scalar) using SSE intrinsics (#405) * Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements * Remove useless space * Address PR feedback * Revert EmitVectorZero32_128 changes
2018-08-14	Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273)	gdkchan

2018-08-05	More accurate impl of FMINNM/FMAXNM, add vector variants (#296)	gdkchan
	* More accurate impl of FMINNM/FMAXNM, add vector variants * Optimize for the 0 case when op1 != op2 * Address PR feedback
2018-07-03	Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). ↵	LDj3SNuD
	Improve CountSetBits8() algorithm. (#212) * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdLogical.cs * Update AVectorHelper.cs * Update ASoftFallback.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Improve CountSetBits8() algorithm. * Improve CountSetBits8() algorithm.
2018-06-28	Add Sse2 fallback to Vector{Extract\|Insert}Single methods on the CPU (#193)	gdkchan

2018-05-11	Add intrinsics support (#121)	gdkchan
	* Initial intrinsics support * Update tests to work with the new Vector128 type and intrinsics * Drop SSE4.1 requirement * Fix copy-paste mistake