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path: root/ChocolArm64/AOpCodeTable.cs
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2018-04-29Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). (#110)LDj3SNuD
* Update ILGeneratorEx.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update Pseudocode.cs * Update Instructions.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdArithmetic.cs
2018-04-25Update AOpCodeTable.cs (#108)LDj3SNuD
2018-04-25Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, ↵LDj3SNuD
Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) * Update AOpCodeTable.cs * Update AInstEmitSimdLogical.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs
2018-04-21Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. ↵LDj3SNuD
(#96) * Update AOpCodeTable.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update Instructions.cs * Revert "Started to work in improving the sync primitives"
2018-04-20Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 ↵LDj3SNuD
Tests. (#92) * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Pseudocode.cs * Update Instructions.cs * Update Bits.cs * Create CpuTestSimd.cs * Create CpuTestSimdReg.cs * Update CpuTestSimd.cs Provide a better supply of input values for the 20 Simd Tests. * Update CpuTestSimdReg.cs Provide a better supply of input values for the 20 Simd Tests. * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs
2018-04-19Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89)MS-DOS1999
2018-04-18Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. (#88)LDj3SNuD
* Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AOpCodeTable.cs
2018-04-12Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77)LDj3SNuD
* Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs
2018-04-08Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & ↵LDj3SNuD
vector) instructions. Add 5 simple tests. (#74) * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update CpuTestSimdArithmetic.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs
2018-04-06Add FMLS (vector) instructiongdkchan
2018-04-05Add FRSQRTS and FCM* instructionsgdkchan
2018-04-05Implement Frsqrte_S (#72)Merry
* Implement Frsqrte_S * Implement Frsqrte_V * Add Frsqrte_S test
2018-04-04Add Faddp (vector) instructiongdkchan
2018-04-04Add PRFM (unscaled) instructiongdkchan
2018-04-04Add FNEG (vector) instructiongdkchan
2018-03-30Enable all ld/st (single structure) instructionsgdkchan
2018-03-30Add BIT instructiongdkchan
2018-03-30Add UABD instructiongdkchan
2018-03-30Add UABDL instructiongdkchan
2018-03-30Add UADDL instructiongdkchan
2018-03-30Add UHADD instructiongdkchan
2018-03-24Add FNMADD instructiongdkchan
2018-03-23Add Cls Instruction. (#67)LDj3SNuD
* Update AInstEmitAlu.cs * Update ASoftFallback.cs * Update AOpCodeTable.cs
2018-03-23Add Frint Instructions and Tests (#62)MS-DOS1999
* add 'ADC 32bit and Overflow' test * Add WZR/WSP tests * fix ADC and ADDS * add ADCS test * add SBCS test * indent my code and delete comment * '/' <- i hate you x) * remove spacebar char * remove false tab * add frintx_S test * update frintx_S test * add ASRV test * fix new line * fix PR * fix indent * Add add_V tests * work on Frintx_V * Add Frintx_V Instruction * add some instruction and test * Syntax + indent * Delete Console Write * Delete Console Write 2 * CR del * Skip NaNs tests * Skip NaNs tests 2 * Fix errors 1 * Fix errors 2
2018-03-16Add BFI instruction, even more audout fixesgdkchan
2018-03-15Add MLA (vector by element), fixes some cases of MUL (vector by element)?gdkchan
2018-03-14Add CRC32 instruction and SLI (vector)gdkchan
2018-03-10Fix EmitScalarUnaryOpF and add SSRA (vector)gdkchan
2018-03-09Add FRINTM (vector) instructiongdkchan
2018-03-09Add SHLL instructiongdkchan
2018-03-06Add SMLAL (vector), fix EXT instructiongdkchan
2018-03-05Add MUL (vector by element), fix FCVTN, make svcs use MakeError toogdkchan
2018-03-05Add FCVTL and FCVTN instruction (no Half support yet), stub SvcClearEventgdkchan
2018-03-02Fix REV64 (vector) instructiongdkchan
2018-03-02Add REV64 (vector) instructiongdkchan
2018-03-02Add EXT, CMTST (vector) and UMULL (vector) instructionsgdkchan
2018-02-24Add FABD (scalar), ADCS, SBCS instructions, update config with better ↵gdkchan
default control mappings, update readme with the new mappings
2018-02-24Fix cpu issue with cmp optimization, add HINT and FRINTX (scalar) ↵gdkchan
instructions, fix for NvFlinger sometimes missing free buffers
2018-02-23Map heap on heap base region, fix for thread start on homebrew, add FCVTMU ↵gdkchan
and FCVTPU (general) instructions, fix FMOV (higher 64 bits) encodings, improve emit code for FCVT* (general) instructions
2018-02-22Add FRINTP instruction, fix opcode ctor call method creation with multithreadinggdkchan
2018-02-20Split main project into core,graphics and chocolarm4 subproject (#29)emmauss
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