| Age | Commit message (Expand) | Author |
|---|
| 2020-10-21 | Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626) | gdkchan |
| 2020-10-13 | Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths... | LDj3SNuD |
| 2020-09-01 | SIMD&FP load/store with scale > 4 should be undefined (#1522) | gdkchan |
| 2020-08-31 | CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492) | LDj3SNuD |
| 2020-08-13 | Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471) | LDj3SNuD |
| 2020-07-19 | Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192) | Valentin PONS |
| 2020-07-17 | CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394) | LDj3SNuD |
| 2020-07-17 | CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390) | LDj3SNuD |
| 2020-07-15 | Fix Decode exception condition (#1377) | Ficture Seven |
| 2020-07-13 | Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335) | LDj3SNuD |
| 2020-07-13 | Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli vari... | riperiperi |
| 2020-06-24 | Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303) | riperiperi |
| 2020-06-18 | Generalize tail continues (#1298) | Ficture Seven |
| 2020-06-16 | Add Profiled Persistent Translation Cache. (#769) | LDj3SNuD |
| 2020-06-14 | VABS takes one input register, not two. (#1300) | riperiperi |
| 2020-05-27 | Add FMaxNmV & FMinNmV Inst.s with Test. (#1279) | LDj3SNuD |
| 2020-05-04 | Implement a new physical memory manager and replace DeviceMemory (#856) | gdkchan |
| 2020-03-24 | Add Fcvtas_S/V & Fcvtau_S/V. (#1018) | LDj3SNuD |
| 2020-03-20 | Move the MakeOp to OpCodeTable class, for reduce the use of ConcurrentDiction... | Chenj168 |
| 2020-03-14 | Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982) | riperiperi |
| 2020-03-12 | Use a Jump Table for direct and indirect calls/jumps, removing transitions to... | riperiperi |
| 2020-03-11 | Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other... | gdkchan |
| 2020-03-10 | Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960) | gdkchan |
| 2020-03-07 | A64 SIMD LDP and STP with size = 0b11 is undefined (#971) | gdkchan |
| 2020-03-05 | Implement Fast Paths for most A32 SIMD instructions (#952) | jduncanator |
| 2020-03-04 | Don't decode blocks starting outside mapped memory & undefined instead of thr... | gdkchan |
| 2020-03-01 | Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954) | gdkchan |
| 2020-03-01 | Implement FACGE and FACGT (Scalar and Vector) AArch64 SIMD instructions (#956) | gdkchan |
| 2020-02-29 | Set Undefined instruction emitter for Undefined property on InstDescriptor (#... | gdkchan |
| 2020-02-24 | Add most of the A32 instruction set to ARMeilleure (#897) | riperiperi |
| 2019-12-14 | Add a limit for the number of instructions in a function (#843) | gdkchan |
| 2019-12-07 | Implemented fast paths for: (#841) | LDj3SNuD |
| 2019-10-24 | Add Sli_S/V & Sri_S/V inst.s (fast & slow paths), with Tests. (#797) | LDj3SNuD |
| 2019-10-04 | Add Tbx Inst. (fast & slow paths), with Tests. (#782) | LDj3SNuD |
| 2019-08-08 | Add a new JIT compiler for CPU code (#693) | gdkchan |
