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Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs102
1 files changed, 24 insertions, 78 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
index 8c4e503e..36120f74 100644
--- a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
@@ -1,4 +1,4 @@
-//#define CcmpReg
+#define CcmpReg
using ChocolArm64.State;
@@ -6,27 +6,21 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
- using Tester;
- using Tester.Types;
-
- [Category("CcmpReg"), Ignore("Tested: second half of 2018.")]
+ [Category("CcmpReg")] // Tested: second half of 2018.
public sealed class CpuTestCcmpReg : CpuTest
{
#if CcmpReg
- [SetUp]
- public void SetupTester()
- {
- AArch64.TakeReset(false);
- }
+ private const int RndCnt = 2;
+ private const int RndCntNzcv = 2;
- [Test, Description("CCMN <Xn>, <Xm>, #<nzcv>, <cond>")]
+ [Test, Pairwise, Description("CCMN <Xn>, <Xm>, #<nzcv>, <cond>")]
public void Ccmn_64bit([Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm,
- [Random(0u, 15u, 1)] uint nzcv,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
+ [Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@@ -37,32 +31,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
- AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Xn));
- AArch64.X((int)Rm, new Bits(Xm));
- Base.Ccmn_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
+ AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
- [Test, Description("CCMN <Wn>, <Wm>, #<nzcv>, <cond>")]
+ [Test, Pairwise, Description("CCMN <Wn>, <Wm>, #<nzcv>, <cond>")]
public void Ccmn_32bit([Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm,
- [Random(0u, 15u, 1)] uint nzcv,
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
+ [Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@@ -73,32 +55,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
- AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
-
- Bits Op = new Bits(Opcode);
- AArch64.X((int)Rn, new Bits(Wn));
- AArch64.X((int)Rm, new Bits(Wm));
- Base.Ccmn_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
+ AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
- [Test, Description("CCMP <Xn>, <Xm>, #<nzcv>, <cond>")]
+ [Test, Pairwise, Description("CCMP <Xn>, <Xm>, #<nzcv>, <cond>")]
public void Ccmp_64bit([Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm,
- [Random(0u, 15u, 1)] uint nzcv,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
+ [Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@@ -109,32 +79,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
- AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Xn));
- AArch64.X((int)Rm, new Bits(Xm));
- Base.Ccmp_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
+ AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
- [Test, Description("CCMP <Wn>, <Wm>, #<nzcv>, <cond>")]
+ [Test, Pairwise, Description("CCMP <Wn>, <Wm>, #<nzcv>, <cond>")]
public void Ccmp_32bit([Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm,
- [Random(0u, 15u, 1)] uint nzcv,
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
+ [Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@@ -145,21 +103,9 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
- AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
-
- Bits Op = new Bits(Opcode);
- AArch64.X((int)Rn, new Bits(Wn));
- AArch64.X((int)Rm, new Bits(Wm));
- Base.Ccmp_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
+ AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-27 09:51:31 +0000