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path: root/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
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Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdHelper.cs')
-rw-r--r--ChocolArm64/Instruction/AInstEmitSimdHelper.cs12
1 files changed, 11 insertions, 1 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
index 1f7a2dad..7716e298 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
@@ -813,6 +813,7 @@ namespace ChocolArm64.Instruction
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int Elems = !Scalar ? 8 >> Op.Size : 1;
+
int ESize = 8 << Op.Size;
int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0;
@@ -823,6 +824,12 @@ namespace ChocolArm64.Instruction
Context.EmitLdc_I8(0L);
Context.EmitSttmp();
+ if (Part != 0)
+ {
+ Context.EmitLdvec(Op.Rd);
+ Context.EmitStvectmp();
+ }
+
for (int Index = 0; Index < Elems; Index++)
{
AILLabel LblLe = new AILLabel();
@@ -867,9 +874,12 @@ namespace ChocolArm64.Instruction
EmitVectorZeroLower(Context, Op.Rd);
}
- EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
+ EmitVectorInsertTmp(Context, Part + Index, Op.Size);
}
+ Context.EmitLdvectmp();
+ Context.EmitStvec(Op.Rd);
+
if (Part == 0)
{
EmitVectorZeroUpper(Context, Op.Rd);