Ryujinx/Ryujinx.Tests/Cpu/CpuTestT32Alu.cs, branch master A backup of the Ryujinx master git branch. Move solution and projects to src 2023-04-27T21:51:14+00:00 TSR Berry 20988865+TSRBerry@users.noreply.github.com 2023-04-07T23:22:00+00:00 cee712105850ac3385cd0091a923438167433f9f 






Removed unused usings. (#3593)
2022-08-18T16:04:54+00:00

Nicholas Rodine
halfofastaple@gmail.com

2022-08-18T16:04:54+00:00

951700fdd8f54fb34ffe8a3fb328a68b5bf37abe

* Removed unused usings.

* Added back using, now that it's used.

* Removed extra whitespace.




* Removed unused usings.

* Added back using, now that it's used.

* Removed extra whitespace.






T32: Implement Data Processing (Modified Immediate) instructions (#3178)
2022-03-06T21:25:01+00:00

merry
git@mary.rs

2022-03-06T21:25:01+00:00

7af9fcbc06d553abe2566a5e150703abc6202956

* T32: Implement Data Processing (Modified Immediate) instructions

* Update tests

* switch -> lookup table




* T32: Implement Data Processing (Modified Immediate) instructions

* Update tests

* switch -> lookup table






T32: Implement ALU (shifted register) instructions (#3135)
2022-02-22T22:11:28+00:00

merry
git@mary.rs

2022-02-22T22:11:28+00:00

7b35ebc64a411e95e197bb36ad4b55c522c3703d

* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)

* OpCodeTable: Sort T32 list

* Tests: Rename RandomTestCase to PrecomputedThumbTestCase

* T32: Tests for AluRsImm instructions

* fix nit

* fix nit 2




* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)

* OpCodeTable: Sort T32 list

* Tests: Rename RandomTestCase to PrecomputedThumbTestCase

* T32: Tests for AluRsImm instructions

* fix nit

* fix nit 2