Ryujinx/ChocolArm64/Decoders, branch master A backup of the Ryujinx master git branch. .NET Core 3.0 is here! (#784) 2019-10-31T18:09:03+00:00 LDj3SNuD 35856442+LDj3SNuD@users.noreply.github.com 2019-10-31T18:09:03+00:00 eee639d6ba544fa5dd9352426d55e91bc54e157d * .NET Core 3.0 is here! * Remove IMemoryManager.cs and its references. * Add T Math/F.FusedMultiplyAdd(T, T, T). Nits. * Nit. * Update appveyor.yml * Revert "Resolve Visual Studio build issues" This reverts commit 1772128ce0fc058e6280001aace3a77a7a96897b. * Update SvcTable.cs 
* .NET Core 3.0 is here!

* Remove IMemoryManager.cs and its references.

* Add T Math/F.FusedMultiplyAdd(T, T, T). Nits.

* Nit.

* Update appveyor.yml

* Revert "Resolve Visual Studio build issues"

This reverts commit 1772128ce0fc058e6280001aace3a77a7a96897b.

* Update SvcTable.cs
Misc cleanup (#708) 2019-07-02T02:39:22+00:00 Alex Barney thealexbarney@gmail.com 2019-07-02T02:39:22+00:00 b2b736abc2569ab5d8199da666aef8d8394844a0 * Fix typos * Remove unneeded using statements * Enforce var style more * Remove redundant qualifiers * Fix some indentation * Disable naming warnings on files with external enum names * Fix build * Mass find & replace for comments with no spacing * Standardize todo capitalization and for/if spacing 
* Fix typos

* Remove unneeded using statements

* Enforce var style more

* Remove redundant qualifiers

* Fix some indentation

* Disable naming warnings on files with external enum names

* Fix build

* Mass find & replace for comments with no spacing

* Standardize todo capitalization and for/if spacing
Refactoring and optimization on CPU translation (#661) 2019-04-26T04:55:12+00:00 gdkchan gab.dark.100@gmail.com 2019-04-26T04:55:12+00:00 8a7d99cdeae2355511d4eb43aefb76d0d886bcf8 * Refactoring and optimization on CPU translation * Remove now unused property * Rename ilBlock -> block (local) * Change equality comparison on RegisterMask for consistency Co-Authored-By: gdkchan <gab.dark.100@gmail.com> * Add back the aggressive inlining attribute to the Synchronize method * Implement IEquatable on the Register struct * Fix identation 
* Refactoring and optimization on CPU translation

* Remove now unused property

* Rename ilBlock -> block (local)

* Change equality comparison on RegisterMask for consistency

Co-Authored-By: gdkchan <gab.dark.100@gmail.com>

* Add back the aggressive inlining attribute to the Synchronize method

* Implement IEquatable on the Register struct

* Fix identation
Implement fixed-point variant of the UCVTF and SCVTF instructions (#578) 2019-02-23T23:52:48+00:00 gdkchan gab.dark.100@gmail.com 2019-02-23T23:52:48+00:00 9679896b9471afdebf860c016d3fd360b9af7f80 * Add fixed-point variant of the UCVTF instruction * Change encoding of some fixed-point instructions to not allow invalid encodings * Fix Fcvtzu_Gp_Fixed encoding * Add SCVTF (fixed-point GP to Scalar) instruction * Simplify *Fixed encodings 
* Add fixed-point variant of the UCVTF instruction

* Change encoding of some fixed-point instructions to not allow invalid encodings

* Fix Fcvtzu_Gp_Fixed encoding

* Add SCVTF (fixed-point GP to Scalar) instruction

* Simplify *Fixed encodings
Implement speculative translation on the CPU (#515) 2019-02-04T21:26:05+00:00 gdkchan gab.dark.100@gmail.com 2019-02-04T21:26:05+00:00 a694420d11ef74e4f0bf473be2b6f64635bc89c7 * Implement speculative translation on the cpu, and change the way how branches to unknown or untranslated addresses works * Port t0opt changes and other cleanups * Change namespace from translation related classes to ChocolArm64.Translation, other minor tweaks * Fix typo * Translate higher quality code for indirect jumps aswell, and on some cases that were missed when lower quality (tier 0) code was available * Remove debug print * Remove direct argument passing optimization, and enable tail calls for BR instructions * Call delegates directly with Callvirt rather than calling Execute, do not emit calls for tier 0 code * Remove unused property * Rename argument on ArmSubroutine delegate 
* Implement speculative translation on the cpu, and change the way how branches to unknown or untranslated addresses works

* Port t0opt changes and other cleanups

* Change namespace from translation related classes to ChocolArm64.Translation, other minor tweaks

* Fix typo

* Translate higher quality code for indirect jumps aswell, and on some cases that were missed when lower quality (tier 0) code was available

* Remove debug print

* Remove direct argument passing optimization, and enable tail calls for BR instructions

* Call delegates directly with Callvirt rather than calling Execute, do not emit calls for tier 0 code

* Remove unused property

* Rename argument on ArmSubroutine delegate
Implement some ARM32 memory instructions and CMP (#565) 2019-01-29T16:06:11+00:00 gdkchan gab.dark.100@gmail.com 2019-01-29T16:06:11+00:00 c1bdf19061ec679aa3c69eda2a41337e3e809014 * Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table 
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)

* Rename some opcode classes and flag masks for consistency

* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations

* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC

* Re-align arm32 instructions on the opcode table
Add ARM32 support on the translator (#561) 2019-01-25T01:59:53+00:00 gdkchan gab.dark.100@gmail.com 2019-01-25T01:59:53+00:00 36b9ab0e48b6893c057a954e1ef3181b452add1c * Remove ARM32 interpreter and add ARM32 support on the translator * Nits. * Rename Cond -> Condition * Align code again * Rename Data to Alu * Enable ARM32 support and handle undefined instructions * Use the IsThumb method to check if its a thumb opcode * Remove another 32-bits check 
* Remove ARM32 interpreter and add ARM32 support on the translator

* Nits.

* Rename Cond -> Condition

* Align code again

* Rename Data to Alu

* Enable ARM32 support and handle undefined instructions

* Use the IsThumb method to check if its a thumb opcode

* Remove another 32-bits check
Misc. CPU improvements (#519) 2018-12-11T00:58:52+00:00 gdkchan gab.dark.100@gmail.com 2018-12-11T00:58:52+00:00 36e8e074c90f11480389560e3f019a161f82efbe * Fix and simplify TranslatorCache * Fix some assignment alignments, remove some unused usings * Changes to ILEmitter, separate it from ILEmitterCtx * Rename ILEmitter to ILMethodBuilder * Rename LdrLit and *_Fix opcodes * Revert TranslatorCache impl to the more performant one, fix a few issues with it * Allow EmitOpCode to be called even after everything has been emitted * Make Emit and AdvanceOpCode private, simplify it a bit now that it starts emiting from the entry point * Remove unneeded temp use * Add missing exit call on TestExclusive * Use better hash * Implement the == and != operators 
* Fix and simplify TranslatorCache

* Fix some assignment alignments, remove some unused usings

* Changes to ILEmitter, separate it from ILEmitterCtx

* Rename ILEmitter to ILMethodBuilder

* Rename LdrLit and *_Fix opcodes

* Revert TranslatorCache impl to the more performant one, fix a few issues with it

* Allow EmitOpCode to be called even after everything has been emitted

* Make Emit and AdvanceOpCode private, simplify it a bit now that it starts emiting from the entry point

* Remove unneeded temp use

* Add missing exit call on TestExclusive

* Use better hash

* Implement the == and != operators
Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516) 2018-12-02T00:34:43+00:00 LDj3SNuD 35856442+LDj3SNuD@users.noreply.github.com 2018-12-02T00:34:43+00:00 ad00fd02442cf9c0f00c4562635738042b521efa * Update OpCodeTable.cs * Update InstEmitSimdShift.cs * Update SoftFallback.cs * Update CpuTestSimdReg.cs * Nit. * Update SoftFallback.cs * Update Optimizations.cs * Update InstEmitSimdLogical.cs * Update InstEmitSimdArithmetic.cs 
* Update OpCodeTable.cs

* Update InstEmitSimdShift.cs

* Update SoftFallback.cs

* Update CpuTestSimdReg.cs

* Nit.

* Update SoftFallback.cs

* Update Optimizations.cs

* Update InstEmitSimdLogical.cs

* Update InstEmitSimdArithmetic.cs
Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484) 2018-10-31T01:43:02+00:00 Alex Barney thealexbarney@gmail.com 2018-10-31T01:43:02+00:00 9cb57fb4bb3bbae0ae052a5af4a96a49fc5d864d * Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment 
* Change naming convention for Ryujinx project

* Change naming convention for ChocolArm64 project

* Fix NaN

* Remove unneeded this. from Ryujinx project

* Adjust naming from new PRs

* Name changes based on feedback

* How did this get removed?

* Rebasing fix

* Change FP enum case

* Remove prefix from ChocolArm64 classes - Part 1

* Remove prefix from ChocolArm64 classes - Part 2

* Fix alignment from last commit's renaming

* Rename namespaces

* Rename stragglers

* Fix alignment

* Rename OpCode class

* Missed a few

* Adjust alignment